A conventional GaN-based FET (Field-Effect Transistor) is known from PTL1 (JP 2012-23074 A), in which with via holes provided in an insulating film formed on finger-like source electrodes and drain electrodes, a source electrode pad and a drain electrode pad are formed so as to be electrically connected to the source electrodes and the drain electrodes, respectively, through the via holes so that a pad-on-element structure is made up for implementation of device compaction.
However, in FETs of the pad-on-element structure, the source-drain parasitic capacitance, i.e. a parasitic capacitance between the source and the drain, tends to become large. A large source-drain parasitic capacitance incurs such failures as ringing in switching operations, decreases in switching speed, increases in switching loss or the like, as a problem.
In another case, PTL2 (JP 2011-29386 A) discloses a semiconductor device in which a normally-ON type GaN FET and a normally-OFF type Si MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) are connected in cascode so as to implement normally-OFF operation.
With this semiconductor device, there is a problem that upon switching from ON to OFF state, the connecting point (cascade connecting point) between the source of the GaN FET and the drain of the Si FET shows such an instantaneous rise in potential that a surge voltage is generated at the cascade connecting point, causing the Si MOSFET of low withstand voltage to be deteriorated and, in some cases, broken down. The surge voltage generated at the cascode connecting point can be considered to be due to the source-drain parasitic capacitance of the GaN FET.